1. Field of the Invention
This invention relates generally to integrated circuit package assemblies and more particularly, it relates to a technique for minimizing signal delays caused by mismatch in length of metal lines on a conventional lead frame and a technique for enhancing the thermal performance of an integrated circuit package assembly via conduction through the package leads.
2. Prior Art
As is generally known in the art, an integrated circuit is formed on a small, substantially planar, piece of semiconductor such as silicon, known as a chip or die. The die generally contains a number of circuits therein and includes a plurality of bonding pads disposed on its top surface adjacent its peripheral edges. In a conventional molded quad flat pack (MQFP) package assembly, the integrated-circuit die is mounted to a centrally-located die-attach paddle or pad, of a thin metal lead frame which is typically stamped or chemically etched from strips of copper-containing materials. The die-attach paddle is rectangular in shape and is supported at each of its four corners by a radially extending support beam.
The lead frame includes a plurality of thin, closely-spaced conductive inner and outer leads which radially extend away from the edges of the die. Each inner lead is integrally connected to a corresponding outer lead. The inner leads are internally connected to corresponding bonding pads of the integrated-circuit die, using wire bonds. The outer leads diverge away from the die and extend through the exterior walls of the molded package where they form the external input/output (I/O) leads for the package assembly. These external leads are then formed to the desired configuration, such as a gull-wing shape, so that the package assembly is adapted to be bonded to bond pads on a printed circuit board (PCB).
The innermost ends of the conductive inner leads are called bonding fingers. Very thin gold bonding wires have their one ends bonded to the corresponding bonding pads on the integrated-circuit die and their other ends bonded to the corresponding bonding fingers. However, due to the rectangular geometry of a die and the converging pattern of the conductive inner leads of the lead frame, the physical length of the conductive inner leads at the corner of the lead frame will always be longer then the length of the leads near the midpoint on the sides of the lead frame.
As a result, the inductance, which is directly proportional to the physical length of the conductive inner lead of the lead frame, will vary from the corner conductive leads to the center conductive leads. Consequently, this will create electrical signal delays between the different conductive leads and thus the time travel or signal speed through these leads will vary from lead to lead, causing a major problem in IC designs. In other words, at high speeds the signal on the center conductive lead of the lead frame will reach the end thereof first. After a certain amount of time delay, the same signal will reach the end of the corner conductive lead.
There are known in the prior art various methods for controlling the clock skew between clock output paths. However, these prior art methods utilize various sophisticated and complex electronic circuits in order to provide an adjustable delay, such as a phase locked loop network or a plurality of delay circuit elements. Thus, these solutions have not been very satisfactory. These prior art methods are more applicable at the die level and not at the package level.
Accordingly, there has arisen a need for an integrated-circuit packaging technique which can compensate for the differences in physical length of the various conductive leads of the lead frame so as to equalize the electrical signal delay between different conductive leads. Further, it would be expedient to provide an integrated-circuit technique which will permit enhanced thermal dissipation characteristics due to better heat transfer via conduction through the package leads of the integrated-circuit package assembly.